At ISCAS 2026, Huawei presented its Tau scaling law and the Kirin 2026 processor with LogicFolding architecture. The proposal does not reduce transistor size, but rather reorganizes the signal flow to shorten internal distances. The result: 238 million transistors per mm², 53.5% higher density, and a 41% improvement in energy efficiency in high-performance cores. A direct response to U.S. restrictions that seeks to bypass the silicon wall without needing extreme lithography.
LogicFolding: folding signals to squeeze the silicon 🧠
The LogicFolding architecture does not shrink transistors, but rather folds data paths to shorten signal transmission. This reduces latency and energy consumption without relying on finer nodes. The high-performance cores of the Kirin 2026 achieve 41% more efficiency, while density reaches figures of 238 million transistors per mm². It is a pragmatic approach: when you cannot use state-of-the-art EUV machines, you redesign the city map instead of building smaller houses.
The trick of folding signals that Intel would like to copy 🤯
While Western manufacturers rack their brains over 1-nanometer lithographies, Huawei arrives and says: Gentlemen, there is no need to shrink, just fold the circuit like origami. And it works. The Kirin 2026 now has the density of a data center packed into a mobile chip. At this rate, competing engineers will start to suspect that Huawei found a dimensional portal in the cleanroom. Or maybe they just use more duct tape.