Researchers at the University of Illinois Urbana-Champaign have presented a method that combines a mathematical design algorithm with electrochemical 3D printing to manufacture pure copper cold plates. These plates, mounted directly onto chips, dissipate heat with unprecedented efficiency, reducing the energy allocated to cooling from the current 30% to just 1.1% of a data center's total consumption. With the rise of AI and the cloud, where data centers are projected to consume up to 12% of the U.S. electrical grid by 2028, this innovation is critical.
Additive manufacturing of microgeometries: the role of pure copper and the topological algorithm 🔥
The key to the advancement lies in topological optimization, an algorithm that refines the geometry of the cold plate fins to maximize heat transfer and minimize the energy required for coolant flow. The resulting shapes are complex, pointed, and feature curvatures impossible to achieve through conventional milling or casting. To materialize them, researchers turn to electrochemical 3D printing, which deposits pure copper layer by layer without the need for high temperatures or supports. This process allows for the fabrication of high surface density structures that multiply the thermal contact area, solving the bottleneck of modern chips, which generate more heat than air can efficiently handle.
Towards passive cooling driven by generative design? ❄️
Beyond immediate energy savings, this technique opens the door to a paradigm where heatsink design is not limited by manufacturing, but by physics. The combination of generative algorithms with electrochemical 3D printing suggests that, in the near future, each chip could have a customized cold plate, optimized for its specific thermal pattern. This would not only reduce the electrical consumption of data centers but also allow for packing more computing power into confined spaces, transforming server architecture and semiconductor microfabrication.
Since electrochemical 3D printing enables cooling geometries that were previously impossible to manufacture, what practical limitations does this technique face in scaling to the mass production of topologically optimized microchannels in high-performance commercial chips?
(PS: 180nm are like relics: the smaller they are, the harder to see with the naked eye)